package chapter03.reg

import chisel3._

class AsyncReg extends Module {
  val io = IO(new Bundle {
    val asyncClk = Input(UInt(1.W))
    val asyncRst = Input(UInt(1.W))
    val out = Output(UInt(8.W))
  })
  val asyncRegInit = withClockAndReset(io.asyncClk.asBool().asClock(),
    io.asyncRst.asBool().asAsyncReset())(RegInit(0.U(8.W)))
  asyncRegInit := asyncRegInit + 1.U
  io.out := asyncRegInit
}
